Part III – March 1969 - Papers- Fabrication Techniques for Germanium MuItieIement Arrays

This paper will describe the development and application of large-scale integration techniques employed in the fabrication of a germanium multielement array. The array consists of 100 by 228 PNP bipolar transistors fabricated on 5 mi1 centers. Back-biased p-n junction techniques are used for electrical isolation of the individual elements. The end use of the array is a high resolution, large area IR sensor. The monolithic array is fabricated in 1 ohm-cm p-type germanium epitaxially deposited on 6 ohm-cm n-type substrate. Epitaxy was accomplished through the hydrogen reduction of germanium te trachloride. Di-borane was used as the dopant. Base regions are achieved by the diffusion of arsenic from doped oxide or arsine sources. Oxide-masking of the arsenic im-pzlvity was achieved by the chemical deposition of a boron doped glass. The emitter is formed by an aluminum alloy diffusion technique. Vacuum deposited aluminum is used for the emitter, interconnections, and for the contact and bonding pads. ALTHOUGH a great volume of literature pertaining to the development of large scale integration techniques (LSI) has been published for silicon and in particular silicon imaging applications,' to date only a small number of similar devices have been constructed using germanium technology.' Since the physical and chemical properties of germanium are vastly different from those of silicon, the fabrication technology for integrated structures in germanium is also different from that of silicon. In particular germanium does not possess a stable oxide as can be grown on silicon by heating in an oxidizing ambient for masking of dopants and passivation. This paper describes the application of germanium LSI techniques employed in the fabrication of a multielement infrared sensor array. The array is used in a high resolution, large area infrared sensor for operation in the 0.8- to 1.5-u spectral range. Back biased p-n junction techniques are used for electrical isolation of individual elements. Discrete germanium devices have been fabricated routinely for some time. However, mainly due to the lack of a suitable mask for selective doping and the high current leakages inherent in germanium p-n isolation, few monolithic germanium structures have been constructed. THE INFRARED MOSAIC A cross-sectional view of the array is shown in Fig. 1. The monolithic structure consists of 12,800 PNP transistor elements in a 100 by 128 matrix fab- ricated on 5 mil centers. The emitters of each line of transistors are connected together using aluminum interconnects while the strip collectors are connected together in series at right angles to the emitter lines. The selection of this structure is dictated by the readout technique involved. Access to each element transistor is obtained by applying a bias voltage to a particular collector strip and separately interrogating each emitter row. A charge storage, i.e., an integration mode is used for reading out this particular array Construction techniques available for use with germanium do not include a selective p-type diffusion capability for surface concentrations greater than 10" per cu cm and junction depths greater than about 10 u. This fact limits the type of structure that may be used. Therefore, an array of PNP transistors that did not employ p-type diffusions was chosen. The structure was fabricated by growing a 1 ohm-cm p-type epitaxial layer on a carefully prepared 6 ohm-cm n-type substrate. N-type dopants were used for the isolation and base diffusions and alloyed aluminum was used to form the emitter junctions. The array was then completed by evaporation of aluminum interconnections and contact pads. SUBSTRATE AND SUBSTRATE PREPARATION Germanium substrates of (111) orientation grown by both Czochralski and zone leveling techniques were utilized for mosaic fabrication. Czochralski substrates were preferred because of the lower dislocation densities available in this type of material. Dislocation densities for the Czochralski material were typically less than 3000 per sq cm, while those for the zone leveled material were typically less than 5000 per sq cm. All substrates were uncompensated to minimize thermal conversion problems in subsequent epitaxial and diffusion processing. Both in-house and vendor polished wafers were used. The in-house polishing technique employed consisted of an initial gross chemical etch in CP4 to remove saw damage from both surfaces. This was followed by a chemical-mechanical polishing operation of one side of the wafer. The chemical-mechanical polishing solution used was Lustrox 1000 (Tizon Chemical Co.), and consists of zirconium dioxide, sodium hypochlorite, water and a surfactant. The wafer thickness before and after polishing was typically 0.020 and 0.010 in, respectively. THERMAL CONVERSION The problem of thermal conversion of both the substrate and epitaxial layer was particularly acute because of the relatively low carrier concentrations employed in both regions. This problem has been encountered by other workers in the past.3 Without special treatment before epitaxial growth substrate conversion (n-type to p-type) and changes in the re-